Interrupt(4): Exception handling & Vector Table

Exceptions occur when:

  • externally generated interrupts
  • an attempt by the processor to execute an undefined instruction
  • accessing privileged operating system functions.

When an exception occurs, control passes through an area of memory called the vector table. This is a reserved area usually at the bottom of the memory map. Within the table one word is allocated to each of the various exception types. This word contains either a branch instruction or, in the case of ARMv6-M and ARMv7-M, an address to the relevant exception handler.

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A vector table consists of a set of ARM instructions that manipulate the PC (i.e. B, MOV, and LDR). These instructions cause the PC to jump to a specific location that can handle a specific exception or interrupt.

Example:  Typical vector table using a literal pool

                AREA vectors, CODE, READONLY
                ENTRY
Vector_Table
                LDR pc, Reset_Addr
                LDR pc, Undefined_Addr
                LDR pc, SVC_Addr
                LDR pc, Prefetch_Addr
                LDR pc, Abort_Addr
                NOP                    ;Reserved vector
                LDR pc, IRQ_Addr
FIQ_Handler
                ; FIQ handler code - max 4kB in size

Reset_Addr      DCD Reset_Handler
Undefined_Addr  DCD Undefined_Handler
SVC_Addr        DCD SVC_Handler
Prefetch_Addr   DCD Prefetch_Handler
Abort_Addr      DCD Abort_Handler
                DCD 0                  ;Reserved vector
IRQ_Addr        DCD IRQ_Handler
                ...
                END

The processor response to an exception

When an exception is generated, the processor performs the following actions:

  1. Copies the CPSR into the appropriate SPSR. This saves the current mode, interrupt mask, and condition flags.
  2. Switches state automatically if the current state does not match the instruction set used in the exception vector table.
  3. Changes the appropriate CPSR mode bits to:
    • Change to the appropriate mode, and map in the appropriate banked out registers for that mode.
    • Disable interrupts. IRQs are disabled when any exception occurs. FIQs are disabled when an FIQ occurs and on reset.
  4. Sets the appropriate LR to the return address.
  5. Sets the PC to the vector address for the exception.

Returning from an exception handler

The method used to return from an exception depends on whether the exception handler uses stack operations or not. In both cases, to return execution to the place where the exception occurred an exception handler must:

  • restore the CPSR from the appropriate SPSR
  • restore the PC using the return address from the appropriate LR.

 

the GIC signals an interrupt exception request to the processor.

gic_id() is executed, to read  ICCIAR to get the interrupt ID. — how kernel find gic_id()?

then gic_id() disables that interrupt in GIC.

for cascaded interrupt, sdma_id is exectured,

interrupt handler(s) are entered.

….

 

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